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(In Mano & Kime unless otherwise noted)
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After peer grading you may turn in the peer
graded assignment (PS #39) for regular grading,
or you may keep it in order to correct it and
then turn it in by 5 PM by placing it in a box
located near Prof. De Boer's office door.
PS#38 and PS#39, which you will turn in for regular
grading on 5/03, will be graded overnight and placed in
the plastic bin labeled "De Boer's Courses" by
noon on Saturday. You may pick up your homework at
your convenience on Saturday afternoon.
After peer grading we will review for the exam
and fill in the course evaluation forms.
5/03
at
5:00 PM
5/04
Do 2-18*, 3-8, 5-7*, 5-15
5/03
5/04
Read 12-1, 12-2, 12-4, and these web pages on
zoned recording and logical block addressing.
Do 12-1*, 12-3, And answer this question:
12-A What are the advantages of packet-based
I/O such as in USB?
Note errata on page 601.
Note errata on problem 12-1*.
5/01
5/03
Do 11-1, 11-2*
4/29
5/01
Review 10-5, Read 10-9, 10-10
Do 10-27*, 10-29
Note errata on problem 10-27*.
4/26
4/29
conditional branching
Read 10-8
Do 10-23*, 10-24, 10-25*
Hint: For Problem 10-23* assume that the
"16 bit register" is named "R".
Also, this supplement can be helpful to
understanding Table 10-7, page 527 in our text.
Hint: For Problem 10-25* a computer does
subtraction A – B as A +
+ 1
(details: text page 345) and assumes the numbers are twos
complement signed integers. Then "borrow" is
the NOT of the carry out of that addtion. This
borrow is saved in the carry flag bit in the
place of the normal carry bit.
4/24
4/26
Read 10-7
Do 10-18, 10-20*, 10-21
Note: On 10-18 work the problem in base ten
using 13 places right of the radix point.
Note: On 10-20* the answer posted on the web
is wrong. The meaning of E is incorrect on the
first and last lines. You should list all the
binary bit patterns possible (e in binary) and
the value of the exponent (E in decimal) in
a style similar to the outer two columns of
Table 10-6 on page 526. Also note carefully
the text underneath Table 10-6.
Note: On 10-21 for part (b) list
E = (the smallest), -1, 0, 1, and (the largest)
values possible. On part (c) the calcuation
should be an estimate in base ten and in
scientific notation, to at least three significant
figures of the largest and smallest positive
normalized numbers.
Optional:
Prof. De Boer offers the links below not that
he expects you to read them all, but rather to
give you an appreciation for the complexity of
representing floating point numbers. Just open
the links and page through them a bit to get a
sense of how much work has been done by
others.
Wikipedia: IEEE Floating Point, a summary
What every CS should know about floating point
Also, journal articles from the 1980's by
Coonen and Stevenson are still relevant.
And the above is just the tip of an iceberg!
4/22
4/24
mapped I/O operations, ALU and shift
instructions, bit manipulation.
Read 10-5, 10-6
Do 10-3*, 10-4, 10-17*
4/19
4/22
Read 10-3, 10-4
Do 10-5, 10-6*, 10-7
Note errata on page 510
4/17
4/19
addressing, stack arithmetic
Read 10-1, 10-2
Do 10-1, 10-2*
Hint: You might find it easier to work on
10-2* first.
For both 10-1 and 10-2*,
SUB and DIV are not described in the text.
Some examples are shown below:
Three Address Instructions:
SUB R1, R2, R3 R1
R2 – R3 DIV R1, R2, R3 R1
R2/R3 Two Address Instructions:
SUB T1, T2 M[T1]
M[T1] –
M[T2] DIV T1, T2 M[T1]
M[T1]/M[T2] One Address Instructions:
SUB X ACC
ACC – M[X] DIV X ACC
ACC/M[X] Hint for 10-2: Part (b) requires only two
temporary memory variables.
Note errata on page 499
4/15
4/17
Read 9-7, 9-8, 9-10
Do 9-12, 9-15
Hints for problem 9-15:
It might be easier to do part (b) first.
For part (a) fill unused fields with "X" for
"don't care." Note that address fields are the
only kind that can be unused since Figure 9-16
shows explicit logic for the other fields.
For part (a), line 3, in "R[5] + 2" the "2" arrives
from the "Constant in" lines to MUX B. (See
Figure 9-15 on page 471.)
In part (a) line 5 let AD = 25 (base ten —
convert it to binary). The value of AD is supplied
in a pair of fields, split to "Left" and "Right." The
left is most significant. This forms effectively a
six-bit field. (See Figure 9-14 on page 467.)
Note errata on problems 9-12 and 9-15.
4/12
4/15
Read 9-4, 9-5, 9-6
Do 9-8*, 9-9 parts a – h (see top of page 492)
Hints on problem 9-9:
Zero can be formed as the exclusive OR of two
identical words. For example, R0 XOR R0 = 0.
Assume numbers are signed integers in the twos
complement number system. Then
_
X - Y = X + Y + 1It is possible that some bits in the control
word do not matter. Mark those as "X" for
"Don't Care"
Although 9-10* is not assigned, understanding
that problem and its solution (posted on the
web) might help you understand and do 9-9.
4/10
4/12
Read 9-1, 9-2, 9-3
Do 9-1, 9-2*
Note: In 9-1, "selection lines" refers to
"Destination Select," "A Select," and "B Select"
Note: For problem 9-2* assume the ALU is
designed to work with numbers in twos
complement format. Overflow detection is
described on page 165 of your text. The result
of your logic should be that N = 1 iff the
output of the ALU represents a negative number.
Bit Z = 1 iff the output represents zero.
Bit V = 1 iff there was an overflow.
Bit C = 1 iff there was a carry out of
the most significant place.
A few of the above statements are counter-
intuitive for some people. For example if the
register contains the number zero, then Z = 1.
(Some people mistakenly think that
if zero is in the register then Z = 0).
4/08
4/10
Read 8-6, 8-7, 8-8
Do 8-9, 8-10, 8-11
4/05
4/08
Read 8-4, 8-5
Do 8-7, 8.8*
Note errata on problems 8-7 and 8-8.
4/03
4/05
RAM operation and signal timing
Read 8-1, 8-2, 8-3
Do 8-1*, 8-2, 8-3* EXCEPT change
"64K X 16" to "1 M x 4" and change
"32000" to "196865." Note: The solution
given online goes with the problem as printed
in the textbook. The assignment is to re-work
the problem with the organization and address
given here.
4/01
4/05
and multiplexers for transfers
Read Ch 7 Sec 7-7, 7-8, 7-14
Do 7-11* Note errata on p404, Problem 7-11*
Note Figure 7-15 too.
7-16 and use hierarcy including a diagram of a
single cell of the register.
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3/29
4/01
Read Ch 7 Sec 7-6 from "Shift Registers" on
page 353 through the end of the Section.
Do 7-4* (Table 7-5 is on page 350), 7-5*, 7-8
Note errata on problem 7-4*
3/25
3/29
Read Ch 7 Sec 7-5, 7-6 up to "Shift Registers"
on page 353.
Do 7-3, 7-B
3/22
3/29
Read Ch 7 Sec 7-1, 7-2, 7-3
Do 7-A (click on link).
Here is a datasheet for the '175 (problem 7-A).
See especilly the function table on page 2 and
the block diagram on the right side of page 2.
(You need to be logged into courses@dordt for
the link to the datasheet to work.)
3/20
3/22
"Programmable" gate arrays
Read Ch 6 Sec 6-3, 6-8
Do 6-9. Answers should be in the style of. . .
"Signal RX at X ns has a <name problem>."
Hint: The times mentioned in the answers always
correspond to a clock edge.
6-15 and also specify how to connect the inputs
X, Y, and Z to the ROM and how to connect the
outputs A, B, C, and D to the ROM.
(Note errata on 6-15),
6-20 except mark fuses to remain intact on the
fuse map for a TIBPAL16L8-25C part. The fuse
map can be found on page 5 of the datasheet.
Note: Discussion of Problem 6-20
3/08
3/22
Review Ch. 4, Read Ch 5 Sec 5-7, 5-10
Do 4.8 part (a) only, also do
5-35 using this state assignment:
A = 00, B = 01, C = 10, D = 11
Note that the problem statement continues on
page 291 underneath Figure 5-45.
Note errata on page 251.
Note errata on page 254.
Note errata on page 259.
3/06
3/08
Review Chapters 4, 5 up to page 240.
Read Ch 5 Sec 5-5 from page 240 to the end.
Do 4-6*, 5-12, 5-13*
Note errata on page 243.
Note: For Problem 4.6, use 7 bit numbers and
perform subtraction as the addition of the
negation of the subtrahend.
Note: Discussion of Problem 5-12
3/04
3/06
Review Ch. 3, Read Ch.5 Sec. 5-5 up to
"Designing With D Flip-Flops" on Page 240.
Do these problems:
3-44 except use a type '138 decoder and
external NAND gates,
also do 5-9, 5-11*
Note: Suggested block symbol for '138 decoder.
3/01
3/04
Review Ch. 3, Ch. 5 Sec 5-3, Read Ch 5 Sec 5-4
Do these problems:
3-13
5-A. Draw a gate-level logic diagram of the SR
master-slave flip-flop shown in Figure 5-9 on
page 216. (Note Figure 5-7 on page 213.)
5-B. (Click on the link.)
5-6 (On page 281 in your text.)
2/27
3/01
Review Ch. 3, Read Ch 5 Sec 5-1, 5-2, 5-3
Do 3-9, 5-1, 5-2, 5-4.
Note: For Problems 5-1 and 5-2 use the input
sequences given in the tables below. Fill in
the outputs shown on these tables. The
complete table or the equivalent information
in a vector waveform file print-out is the
answer.
_ _ _ _
S R | Q Q C S R | Q Q
-----+----- --------+-----
1 1 | 0 0 0 |
1 0 | 0 0 1 |
0 1 | 0 1 0 |
1 1 | 0 1 1 |
0 1 | 1 0 1 |
0 0 | 1 0 0 |
0 1 | 1 1 0 |
1 0 0 |
Table for 5-1 1 1 0 |
1 1 1 |
1 1 0 |
1 1 1 |
1 0 0 |
Table for 5-2
Note: Discussion of Problems 5-1 and 5-2 Optional supplemental reading: RS Nand Latches.
2/25
2/27
Review Ch 2, Read Ch 4 Sec 4-6, 4-7, 4-9
Do 2-26, 4.23
Hint: Although 4-20* is not assigned, look at
that problem statement and its solution which
is posted on the web.
Another Hint: The sentence, "Note that
complemented inputs are available." means that
although the signal a_n is a separate input
from a, you should assume that a_n is always
the logical not of a. Wherever you might like
to use
you
should instead use the signal a_n. The same goes for the other similarly
named pairs of signals.
2/22
2/27
Incrementing, Sign extension, etc.
Review Ch 2, also Section 4-4,
Read Ch 4 Sec 4-5
Do 2-17,
Do 4-4 except do it in this order:
1.) The given numbers are unsigned binary.
Pad each with leading zeros until it is
eight bits wide. This converts the
numbers from unsigned binary to signed
two's complement (and all of them are
positive).
2.) Negate subtrahends by taking the
two's complement.
3.) Add. The result is the answer without
any further manipulation. The answer is
in the two's complement notation.
4.) For each case, note if there is
"overflow" or "no overflow."
Do 4-45 Note: this problem is not in the
textbook, click the link to view it.
2/20
2/22
Integers, overflow vs. carry-out
Review Ch 1. Read Ch 4 Sec 4-4
Do 1-17 and prove your answer,
4-2* (Use manual verification),
4-3* and note errata on 4-3*
Also for each note if there is overflow or not.
Definition: Overflow upon negation occurs iff
negating a non-zero number does not change
the sign of the number.
Note that by definition the number zero cannot
overflow upon negation. (–0 = +0 = 0)
Note: In 4-3* the given numbers are mostly
negative since most start with a 1 bit.
Note errata on Page 166
Note errata on Problem 1-17
2/18
2/20
binary subtraction, signed integers
Read Ch 4 Sec 4-1, 4-2, 4-3
Do 4-1 except begin with a truth table, then
use K-maps to derive equations for outputs
C2, S1, and S0. Stop with equations in SOP form
since drawing a schematic will be too tedious.
Note that the inputs are A1, A0, B1, B0, and C0.
You will need five-variable K-maps for this
problem. Hint: Drawing the K-maps in a
horizontal style works best for this problem.
FYI "Karmah" is an online Java applet that can
do K-maps up to 8 inputs. It uses a slightly
different style (overlays) than Prof. De Boer
illustrated in class.
Optional Reading on five-variable K-maps.
Explains both the gray code style preferred by
Prof. De Boer (so that "folding" works) and
the overlay style that generalizes (poorly) to
even larger K-maps.
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2/15
2/20
Read 3-8, 3-9, 3-10
Do 3-35*, 3-42*, 3-46, 3-47*
2/11
2/15
Read 3-5, 3-6, 3-7
Do 3-21, 3-24, 3-25,
3-32 except use a type '138 decoder and NAND
(instead of OR) gates.
Hint 1) Send a logic-1 to a LED to turn it on.
Hint 2) Read part (b) before doing part (a).
Hint 3) Use a block symbol for the '138
decoder rather than drawing all the gates.
This decoder is identical in function to the
the one shown in your text in Figure 3-33.
Note that input A is the least significant.
Hint 4) Use value fixing on unneeded gate inputs.
Note: Professor De Boer assigned this problem
because it poses an interesting technical
challenge, but he does not endorse gambling.
Note errata on Figure 3.33
2/06
2/11
maunal verification
Read Ch 3 Sec 3-2, 3-3, 3-4
Do 3-2*, 3-16, 3-20
2/04
2/06
Read Ch 2 Sec 2-11, Review all of Ch 2
Read Ch 3 Sec 3-1
Do 2-8, 2-30, 3-1
Note errata on problem 2-30
2/01
2/04
Read Ch 2 Sec 2-8, 2-9, 2-10, Review 2-5
Do 2-24, 2-25*, 2-34
1/30
2/01
Read Ch 2 Sec 2-5, 2-6, 2-7
Do 2-15*, 2-16, 2-19*, 2-31
1/28
2/01
Two-level logic
Read Ch 2 Sec 2-3, 2-4
Do 2-10*, 2-11, 2-12*, 2-14
Note errata on the answer to Problem 2.11*
Note errata on the answer to Problem 2-12*
Note errata on page 60, Figure 2-9(b)
Note on 2-14: "Optimize" means to "simplify"
as shown by several examples in section 2-4.
1/25
1/25
Read Ch 2 Sec 2-1, 2-2
Do 2-1*, 2-2*, 2-7*
1/23
1/25
Read Ch 1 Sec 1-4 through 1-7
Also read about binary prefixes from NIST
Optional--read more about binary prefixes here.
Do 1-10*, 1-22, 1-24, 1-25*
Note errata on page 23.
Note errata on problem 2-10
1/21
see
note
3
Scan Chapter 1. Read Sections 1-2, 1-3
Do 1-4, 1-5, 1-6, 1-7*, 1-8, 1-9*
Note: The answer to 1-5 must be exact.