Dordt College Engineering & Department |
A FEW WORDS ABOUT THE 74LS138 DECODER AND FIGURE 3-33 ON PAGE 144 IN OUR TEXTBOOK |
However, the author of our textbook took out some double negations and made some other minor changes to make the logic easer to understand, compared to the actual commercially available part. You can view the actual schematic of real parts on any of a number of datasheets for these parts. For example, in Fairchild's datasheet, see the lower left quadrant of page 2. In this datasheet you can see that each input to the part goes to only one logic gate. The non-inverted inputs are derived from the inverted inputs by another set of inverters. This reduces the amount of current that flows through each input pin, but it has no effect on the logical outcome. The author of our textbook choose to ignore this detail and removed the extra inverters from his schematic. If built as shown in our textbook however, the decoder would cause more heating of the chips connected to it because of the increased current flow through it's input pins. You can use either schematic since logically they are equivalent. (Use our textbook's because it is simpler!) Since the '138 part has "negative true outputs" (all outputs are logic-1 except the single output that is addressed—see the "function table" in the datasheet linked above) you will need to use a NAND gate to functionally OR a set of minterms together. This is the case because a logic-0 on any input to a NAND gate will force the output of the gate to go to logic-1.
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