DORDT UNIVERSITY ENGINEERING DEPARTMENT PROBLEM SETS (Last update 12/13/2019 7:38 pm)
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PS # | Due |
Problems Assigned
(In Mano & Kime unless otherwise noted)
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12/10 is the last day of class—no new assignment. After peer grading you may turn in the peer graded assignment (PS #26) for regular grading, or you may keep it in order to correct it and then turn it in by 5 PM by placing it in the bin located near Prof. De Boer's office door. PS#25 and PS#26, which you will turn in for regular grading on 12/10, will be graded overnight and placed in the plastic bin near De Boer's office door by noon on Wednesday. You may pick up your homework at your convenience after that. Look for an envelop with your your name on it in the plastic bin. After peer grading we will review for the exam and fill in the course evaluation forms. |
26
| 12/05 |
12/10 12/10 at 5:00 pm | 12/13 |
Topics: Assembly language, addressing modes,   arithmetic via a stack Read Ch 9 Sec. 9-1 through 9-5 |
25
| 12/03 |
12/05 12/10 | 12/13 |
Topics: Single-cycle sequencer,   Instruction formats, Instruction decoder Read Ch 8 Sec 8-7 through 8-8 Note errata on Problem 8-15 Hints for problem 8-15: It might be easier to do part (b) first. For part (a) fill unused fields with "X" for "don't care." Note that address fields are the only kind that can be unused since Figure 8-16 shows explicit logic for the other fields. For part (a), line 3, in "R[5] + 2" the "2" arrives from the "Constant in" lines to MUX B. (See Figure 8-15 on page 460.) The "Zero Fill" unit Pads the constant with zeros in the more significant places. In part (a) line 5 let AD = 25 (base ten — convert it to binary). The value of AD is supplied in a pair of fields, split to "Left" and "Right." The left is most significant. This forms effectively a six-bit field. (See Figure 8-14 on page 456.) The small letters "se" stand for "sign- extended." This means that the word will be padded up to its final width by copying the sign bit into the more significant places. |
24
| 11/26 |
12/03 12/05 | 2/10 |
Topics: Datapath of a CPU, Control word Read Ch 8 Sec 8-1 through 8-6 Note: For Problem 8-2* assume the ALU is designed to work with numbers in twos complement format. Overflow detection is described on pages 171-172 of your text. The result of your logic should be that N = 1 iff the output of the ALU represents a negative number. Bit Z = 1 iff the output represents zero. Bit V = 1 iff there was an overflow. Bit C = 1 iff there was a carry out of the most significant place. A few of the above statements are counter- intuitive for some people. For example if the register contains the number zero, then Z = 1. (Some people mistakenly think that if zero is in the register then Z = 0). Further note on Problem 8-2*: The problem references "outputs F7 through F0." However in the textbook figures, such as Figures 8-1 through Figure 8-6, the outputs of an ALU are usually labeled Gi, not Fi." It does not matter how the output of an ALU is labeled. Just be aware of the actual ALU outputs available to solve this problem. |
23
| 11/21 |
11/26 12/03 | 12/05 |
Topics: Memory, ROM timing, SRAM, DRAM, ECC Read Ch 7 Sec 7-3, 7-4, 7-7, Slides on Hamming Note errata on Problem 7-7 |
22
| 11/19 |
11/21 11/26 | 12/03 |
Topics: Memory, ROM, PLA, PAL Read Ch 7 Sec 7-1, 7-2, Ch 5 Sec 5-2 |
21
| 11/14 |
11/19 11/21 | 11/26 |
Topics: Tri-state gates (outputs)   Register transfers via tri-state logic   Register transfer notation Read Ch 6 Sec 6-8 |
20
| 11/12 |
11/14 11/19 | 11/21 |
Topics: Register types,   register-cell (bit-slice) schematics Read Ch 6 Sec 6-5, 6-6, 6-7 Note 1: Note errata on Problem 6-3. Note 2: The online solution to 6-5 is insufficient because it has no schematic at all. Also, Figure 6-11 is not drawn in a conventional bit-slice style. Present your answer in the bit- slice style demonstrated in class on 11/12. |
19
| 11/07 |
11/12 11/14 | 11/19 |
Topics: Defn of Register, Defn of μop   bit-slice style schematics Read Ch 6 Sec 6-1, 6-2, 6-3, 6-5 Hint #1: In order to, "Draw the logic diagram" you will save yourself lots of time by drawing a bit- slice and then drawing the block symbol. (Reduces the amount to draw almost by a factor of four.) Hint #2: A 4:1 multiplexer can be really helpful in the bit-slice. You may draw it as a block-entity if it is properly labeled. Clarifications: The, "no change" μop means the register should just store the present data. The, "Complement output" μop means that the the data stored should be replaced with the complement of the present data stored. |
18
| 11/05 |
11/07 11/12 | 11/19 |
Topics: State Machine Diagrams, One-Hot state   assignments, clock speed, metastability Read Ch 4 Sec 4-5, 4-6 |
17
| 10/31 |
11/05 11/07 | 11/12 |
Topics: Mealy & Moore , State Diagrams Review Ch 4 Sec 4-4 |
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| 10/29 |
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Study for the test on Thursday, 10/31 No homework or peer grading is due on 10/31 Details are published on Canvas regarding the material covered on the test, allowable crip sheet, calculators, etc. |
16
| 10/24 |
10/29 11/05 | 11/12 |
Topics: Mealy & Moore, State Diagrams Read Ch 4 Sec 4-4 |
F16
| 10/22 |
10/24 10/29 | 11/05 |
Topics: Hardware description languages (HDL)   Finite State Machines Read Ch 2 Sec 2-8, 2-9, Ch 4 Sec 4.4 |
E16
| 10/17 |
10/22 10/24 | 10/29 |
Topics: Async vs. sync., latch vs. FF, D-FF detail Read slides from 10/17, Sec. 4-3, 4-9 Hints: Figures 4-8 and 4-10 are relevant to this problem. Assume that "Initially, all storage elements store 0." because the circuit randomly settled to this state upon power-up. (This is not especially likely, but the authors set the problem up this way.) Note that the D-flip-flop in this is positive-edge triggered whereas the flip-flop analyzed in class was negative-edge triggered. The rules discussed in class will need some minor changes in order to make them work in this case. |
D16
| 10/15 |
10/17 10/22 | 10/24 |
Topics: Static memory, NAND-, D-latches, bubbles Read slides from 10/15, Sec. 4-1, 4.2 The problems can be downloaded from the links. |
C16
| 10/10 |
10/15 10/17 | 10/22 |
Topics: twos' comp., offset binary Read slides from 10/10, Sec. 3-9, thru 3.12 Hints for Problem 3-55: 1.) All the given numbers are in the 2C form, regardless of their algebraic sign! (But yes, the negative numbers are in 2C form if you need a reminder.) 2.) Do the addition or subtraction in an 8-bit word. 3.) To change the bit-width of a 2C number you need to use sign extension. See textbook page 182. Problem 3-97 can be downloaded from the link. |
B16
| 10/08 |
10/10 10/15 | 10/17 |
Topics: unsigned, signed mag., ones' comp. Read Classroom slides from 10/08 (Each problem number is a link.) |
A16
| 10/01 |
10/08 10/10 | 10/15 |
Topics: BCD addition, Signed integers Read Ch 1 Sec 1-5, Classroom slides from 10/01 (Each problem number is a link.) |
9
| 9/24 |
10/01 10/08 | 10/10 |
Topics: Value Fixing, Vectors (Busses), Decoders   Encoders, Multiplexers, partitioning Read Chapter 2, Section 2.6, 2.7, Chapter 3 Sections 3-1 through 3-6. Note errata on pages 127-128, Example 3-5. |
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| 9/24 |
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Study for the test on Thursday, 9/26 No homework or peer grading is due on 9/26 Details are published on Canvas regarding the material covered on the test, allowable calculators, etc. |
8
| 9/19 |
9/24 10/01 | 10/03 |
Topics: Decoders, Encoders Read Chapter 2, Section 2.6, 2.7, Chapter 3 Sections 3-1 through 3-6. Note errata on pages 127-128, Example 3-5. |
7
| 9/17 |
9/19 9/24 | 10/01 |
Topics: Application of implicant tables to K-maps Read classroom slides (topic is not in textbook) (Each problem number is a link.) |
6
| 9/12 |
9/17 9/19 | 9/24 |
Topics: Incompletely specified functions Read Ch 2 Sec 2-5 from page 75 "Don't Care..." to the end of the Section. Note errata on the answer to Problem 2-25* |
5
| 9/10 |
9/12 9/17 | 9/18 |
Topics: Karnaugh maps (K-maps) and optimizaton Read Sec 2-4, 2-5 up to page 75, "Don't Care..." Note on 2-14: "Optimize" means to "reduce to SOP or POS form" as shown by several examples in section 2-4. |
4
| 9/05 |
9/10 9/12 | 9/17 |
Topics: Duality, Definitions of   variable, literal, term, sum term,   SOP, POS, SSOP, SPOS, Σm, ΠM   Grey code Read Ch 1, Section 1-7, Ch 2 Sec 2-3, Note errata on the answer to Problem 2-12* |
3
| 9/03 |
9/05 9/10 | 9/12 |
Topics: Gates and Boolean logic Read Ch 2 Sec 2-1, 2-2 Note that the problem statement for 2-7* condinues at the top of textbook page 104. |
2
| 8/29 |
9/03 9/05 | 9/12 |
Topics: Coded information, eg. BCD, ASCII Read Ch 1 Sec 1-4 through 1-7 Also read about binary prefixes from NIST Optional--read more about binary prefixes here. Note errata on problem 1-10 Note errata on problem 1-24 |
1
| 8/27 |
8/29 9/03 |
9/05 see note 3 |
Topics: Binary numbers, Arithmetic in binary Scan Chapter 1. Read Sections 1-2, 1-3 Note: The answer to 1-5 must be exact. |
0
| 8/27 |
never see note 6 |
8/26 |
Topics: Binary numbers, Arithmetic in binary Scan Chapter 1. Read Sections 1-2, 1-3 Do 1-2, 1-11* Note: You do not actually have to do this assignment. This assignment provides an example solution. You may wordprocess or hand-write your solutions. |
Note 1) |
Homework must be ready for peer grading and discussion in
class on the first listed due date. It must be turned in for a
final grade on the second listed due date. Peer grading will be
1/5 (20%) of the homework grade.
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Note 2) |
Problems marked with an asterisk (*) have solutions available
on the textbook's companion website.
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Note 3) |
If a "Returned" date is given and is a link (gold), then
solutions to the corresponding problem set are available to
students currently enrolled in the course. The links are
served by the courses@dordt system. If you click the link
and get a login screen, use your usual courses@dordt login.
If that does not get you the solutions, then use your browser's
back button (or alt-left-arrow on the keyboard) twice to get
back to the this page and try again. The link only works
after you are logged in to courses@dordt.
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Note 4) |
Problems sets shown above with no "assigned" date are
tentative. More problems might be added, expected due dates
might change, but problems shown will eventually be assigned.
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Note 5) |
If you are having difficulty reading the latest version of this
page it may have to do with your browser's cached memory. Read
this note on
cached pages to solve the problem.
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Note 6) | Problem Set #0 is an example. You do not need to solve these problems. An MS Word document that can be optionally used as a template can be downloaded here: 204F19PS0_DDB_blank.docx |