Further discussion of problems 5-1 and 5-2

The tables given above for problems 5-2 and 5-1 contain a few challenges. On the first line of each table it is not possible to know what Q will be. Just label that output U where U could be a logic-0 or a logic-1. Then what will be? (It could be either U or
.) In some following lines the same problem occurs. Handle them the same way. If you used Quartus II to run this simulation note that it gives an undefined output in these cases.

In the last line of the table for 5-2 two input bits change at the same time, which is not allowed for a simulation of this type. Flag this by noting that the outputs will be unknown. If you used the Quartus II simulator to do this problem, what does Quartus II do in this situation? (An automatic simulation cannot catch this problem. With no warning it gives a result but the result is unreliable.)

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