Read Sections 4-7, 4-9

Comments on Section 4-7 in Mano & Kime 3rd edition.

You may want to review the "VHDL Exercise" in the Lab 4 handout in light of this section. If you have any questions, bring them to class. You should recognize that the lab exercise made use of a "Structural Description."

Since we use TTL chips and Altera's programmable CPLD in our lab, the Altera Maxplus2 library is more appropriate to our situation than the generic lcdf_vhdl library suggested in our text. Since the port maps and component names are not exactly the same in each library, one library is not a literal substitute for the other. When we use the Maxplus2 library we must specify the TTL part numbers for the functions (e.g. a_7400) rather than the generic names (e.g. NAND2). Some of the generic parts in the lcdf_vhdl library have no TTL equivalents and thus cannot be built on a breadboard in our lab.

A key new concept introduced in this section is the "Dataflow Description." No homework is assigned on this topic, just read it and see what you can get from it.

Our text does not use the common conventions for capitalization in VHDL code. This is not important since VHDL is case insensitive.

The assignment to go along with the reading.

Do 4-36 with these changes:

  1. Use the Altera Maxplus2 library instead of lcdf_vhdl. You will not need to "compile" the Maxplus2 library--that was already done when Quartus II was installed.


  2. In Quartus II the "Generate Functional Netlist" command will "Compile" your VHDL file.


  3. You may use this given MK4_36.vwf vector waveform file or write you own. If you write your own it must conform to the list given in the problem statement in your text.


  4. Note this errata:
    In the problem statement replace "E_n, A0, A1" with "E_n, A1, A0."


  5. Hand in a print-out of your VHDL code and a printout of the simulation's vector waveform file showing the four output signals as simulated. (With the "Simulation Report" open and having the focus, select "File | Print" and in the Print list select "Simulation Report | Simulator | Simulation Waveforms.)

HINTS

  1. It is easiest if the project directory, project name, and top-level entity are all the same. As given in Figure 4-27, it is a long name (23 characters).


  2. You may download the code in Figure 4-27 from the book's companion web site. Right-click on decoder_2_to_4_w_enable.vhd and save target as that file name in your project folder. You will need to edit the file name to make it correct before you save it. In the file name your web browser gives you, change "_st" to "_w_enable". Also be sure the extension is "vhd".


  3. You may write a first draft of your VHDL code using any text editor. Windows Notepad for example, works fine for this.


  4. The Quartus II program is installed and supported on the computers in the EE lab which you may use at any time when the engineering building is open and a workstation is free, except that scheduled labs have priority. You may also download and install a copy of Quartus Web edition on your own computer. Students can get a free license to use the software for a limited time--about six months. The license is renewable for free too.


  5. The components in the Altera library do not have the same names as those in the lcdf_vhdl library. Note. . .
    a_7400 is a 2-input NAND gate,
    a_7404 is an inverter, and
    a_7408 is a 2-input AND gate.
    Make appropriate changes in the VHDL code for the decoder. (Don't attempt to change the library to match the decoder. Instead, change the decoder to match the library.)


  6. The port lists in the component statements of the decoder need to be changed to match those of the actual components used from the library. If you cut and paste the component statements from the library into the decoder's VHDL code (and delete the existing component statements) you will avoid typos. The libraries are typically found at
    "c:\program files\altera\quartus41\libraries\vhdl. . ."


  7. The port map statements in the given VHDL code use an alternative syntax. To use the syntax introduced in the lab, just delete all the "in1 =>" and similar characters. For example,
    8. g0: NOT1 port map (in1 => A0, out1 => A0_n);
    becomes
    g0: a_7404 port map (A0, A0_n);
    Here the entity "NOT1" from the lcdf_vhdl library was also replaced with the "a_7404" entity from the Maxplus2 library.

  8. Professor De Boer discourages the use of the alternative syntax because then more editing is needed when a library is changed. (The editing is needed to change or remove the signal names internal to the component, such as "in1". The syntax De Boer recommends connects to the signals internal to the component automatically by inference from the component port list).


  9. priority_encoder_4_input.vhd is an example file ready-to- simulate. It illustrates the use of structural components from the Maxplus2 library. It is a VHDL file equivalent to Figure 4- 12 on page 155 of your text, and it uses a structural description of the logic. If you actually want to try running that simulation, set up a project of that name and use the priority_encoder_4_input.vwf for the simulation input. Actually simulating this file is not necessary. Just looking at the VHDL code might help you work the assigned problem.


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